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IC Package Combined IC and Systems Package Optional Package 1
Systems Package PCB Studio Supported Machine Types
   


IC Package:

From IUS 8.1.006-sUSR1:
Verifault®-XL simulator 64bit Verifault®-XL simulator
Cadence® Export Model Packager AMS Designer with Flexible Analog Simulation
From IPCM Hotfix 8.1.004:
Incisive Plan-to-Closure Methodology Option
From EMGR 8.1003:
Incisive Enterprise Manager
From SPMN 8.1.003:
Incisive Enterprise Specman ESL Testbench
From IFV Hotfix 8.1.004:
Incisive Formal Verifier
From ABVIPAHB 1.0:
AMBA AHB Assertion Based VIP
From ABVIPAXI 1.0:
AMBA AXI Assertion Based VIP
From ABVIPOCP 2.2:
OCP-IP Assertion Based VIP
From UVCAMBA 2.4:
AMBA AHB UVC
From UVCAXI 1.4:
AMBA AXI UVC
From EVCETH 2.2:
e Verification Component (eVC) for Ethernet protocol
From EVCPCI 2.2:
e Verification Component (eVC) for PCI 2.2/2.3 protocol
From UVCPCIE 3.0:
PCI Express 2.0 End Point UVC PCI Express 2.0 Root Complex UVC
From UVCUSB 2.5:
USB UVC
From ANLS 7.1 USR2:
Dynamic Gate Option to VoltageStorm PE VoltageStorm PE
From ASSURA3.1.7 USR2HF10_CDB:
Assura(TM) Design Rule Checker Assura(TM) Layout Vs. Schematic Verifier
Assura(TM) Parasitic Extractor Assura(TM) RCX Field Solver Option
Assura(TM) RCX Parasitic Inductance Option Assura(TM) RCX Multiprocessor Option
Assura(TM) RCX High Frequency Option RCX Advanced process features
Assura(TM) Multiprocessor Option
From ASSURA3.1.7 USR2HF7OA_612:
Assura(TM) Design Rule Checker Assura(TM) Layout Vs. Schematic Verifier
Assura(TM) Parasitic Extractor Assura(TM) RCX Field Solver Option
Assura(TM) RCX Parasitic Inductance Option Assura(TM) RCX Multiprocessor Option
Assura(TM) RCX High Frequency Option RCX Advanced process features
Assura(TM) Multiprocessor Option
From CCD 7.2 s300:
Encounter Conformal Constraint Designer - XL
From CONFRML 7.2 Hotfix s340:
Encounter Conformal Low Power - GXL Encounter Conformal ECO Designer
From ET 7.2.4:
Encounter(R) True-time Test - GXL Encounter(R) Test Architect - GXL
Encounter Diagnostics Environment - XL Encounter Diagnostics Engine - XL
From ETS 7.1 USR3-s218_1:
Encounter Library Characterizer - GXL Encounter Timing System-GXL
From EXT 7.12:
Virtuoso QRC Extraction - GXL
From IC 5.1.41 Hotfix 122:
Cadence(R) Design Framework II Cadence(R) Design Framework Integrator's Toolkit
64bit Cadence(R) Design Framework Integrator's Toolkit Virtuoso(R) Preview
Virtuoso(R) Simulation Environment Virtuoso(R) Schematic VHDL Interface
Virtuoso(R) Schematic Editor Verilog(R) Interface Virtuoso(R) Schematic Editor HSPICE Interface
64bit Virtuoso(R) Layout Editor Virtuoso(R)-XL Layout Editor
Virtuoso(R) Compactor Virtuoso LE Turbo Basic
Virtuoso(R) Analog Oasis Run-Time Option Cadence(R) OASIS for RFDE
Virtuoso(R) Electronic Design for Manufacturability Option Spectre(R) Third-party Simulator Interface
Spectre(R) Verilog-A Simulation Option Spectre(R)/-RF - Cadence(R) SPW Model Link Option to Spectre(R) RF
Spectre(R)-RF IC Package Modeler Option Virtuoso(R) Analog HSPICE Interface Option
Virtuoso(R) Schematic Editor Virtuoso(R) Analog Design Environment
Spectre(R)-RF Substrate Coupling Analysis Option Virtuoso(R) Analog VoltageStorm Option
Virtuoso(R) Analog ElectronStorm Option Virtuoso(R) Layout Migrate
Structure Compiler Virtuoso(R) Schematic Composer to design compiler integration
Cadence(R) RC Network Reducer Option Virtuoso(R) AMS Designer Environment
Dracula(R) Design Rule Checker 64bit Dracula(R) Design Rule Checker
Dracula(R) Layout Vs. Schematic Verifier 64bit Dracula(R) Layout Vs. Schematic Verifier
Dracula(R) Parasitic Extractor 64bit Dracula(R) Parasitic Extractor
64bit Diva(R) Design Rule Checker Diva(R) Layout Vs. Schematic Verifier
64bit Diva(R) Layout Vs. Schematic Verifier Diva(R) Parasitic Extractor
Cadence(R) SKILL Development Environment Virtuoso(R) EDIF 300 Connectivity Reader/Writer
Virtuoso(R) EDIF 300 Schematic Reader/Writer 64bit Virtuoso(R) STREAM Interface
Cadence(R) team design project administrator
From IC IC 6.1.3:
Cadence(R) Design Framework II Cadence(R) Design Framework Integrator's Toolkit
64bit Cadence(R) Design Framework Integrator's Toolkit Virtuoso(R) Simulation Environment
Virtuoso(R) Schematic VHDL Interface Virtuoso(R) Schematic Editor Verilog(R) Interface
Virtuoso(R) Schematic Editor HSPICE Interface Virtuoso(R) Analog Oasis Run-Time Option
Cadence(R) OASIS for RFDE Virtuoso(R) Analog HSPICE Interface Option
Virtuoso(R) Analog VoltageStorm Option Virtuoso(R) Analog ElectronStorm Option
Virtuoso(R) Layout Migrate Cadence(R) RC Network Reducer Option
Virtuoso(R) AMS Designer Environment Dracula(R) Design Rule Checker
64bit Dracula(R) Design Rule Checker Dracula(R) Layout Vs. Schematic Verifier
64bit Dracula(R) Layout Vs. Schematic Verifier Dracula(R) Parasitic Extractor
64bit Dracula(R) Parasitic Extractor Diva(R) Design Rule Checker
64bit Diva(R) Design Rule Checker Diva(R) Layout Vs. Schematic Verifier
64bit Diva(R) Layout Vs. Schematic Verifier Diva(R) Parasitic Extractor
Cadence(R) SKILL Development Environment Virtuoso(R) EDIF 200 Reader
Virtuoso(R) EDIF 200 Writer Virtuoso(R) Schematic Editor XL
Virtuoso(R) Analog Design Environment - GXL Virtuoso(R) Visualization & Analysis XL
64bit Virtuoso(R) Layout Suite L Virtuoso(R) Layout Suite - GXL
Virtuoso Constraint API Run-Time Option CDLIN
PostScript Level 2 Hardcopy Output
From ICC 11.2.41 Hotfix 60:
Virtuoso(R) Chip Assembly Router
From MMSIM 7.01 Hotfix 076:
Virtuoso(R) Spectre Model Interface Option Spectre(R)/-RF - Cadence(R) SPW Model Link Option to Spectre(R) RF+G199
Virtuoso(R) UltraSim Full-chip Simulator Virtuoso(R) RelXpert
Cadence Virtuoso Passive Component Designer Virtuoso Spectre GXL
From AES 1.0:
Cadence Advanced Encryption Standard-64bit
From RFDSGN 3.0.3.001:
Virtuoso RF Designer
From REL SOC 7.1 USR3-s219_1:
SoC Encounter - GXL

Systems Package:

From IUS 8.1.006-sUSR1:
Verifault(R)-XL simulator 64bit Verifault(R)-XL simulator
Cadence(R) Export Model Packager AMS Designer with Flexible Analog Simulation
From IPCM Hotfix 8.1.004:
Incisive Plan-to-Closure Methodology Option
From EMGR 8.1003:
Incisive Enterprise Manager
From SPMN 8.1.003:
Incisive Enterprise Specman ESL Testbench
From IFV Hotfix 8.1.004:
Incisive Formal Verifier
From ABVIPAHB 1.0:
AMBA AHB Assertion Based VIP
From ABVIPAXI 1.0:
AMBA AXI Assertion Based VIP
From ABVIPOCP 2.2:
OCP-IP Assertion Based VIP
From UVCAMBA 2.4:
AMBA AHB UVC
From UVCAXI 1.4:
AMBA AXI UVC
From EVCETH 2.2:
e Verification Component (eVC) for Ethernet protocol
From EVCPCI 2.2:
e Verification Component (eVC) for PCI 2.2/2.3 protocol
From UVCPCIE 3.0:
PCI Express 2.0 End Point UVC PCI Express 2.0 Root Complex UVC
From UVCUSB 2.5:
USB UVC
From SPB Hotfix 16.01.016:
Cadence(R) SKILL Development Environment Allegro(R) System Architect - GXL
Allegro(R) PCB Partitioning option (SPARC/Solaris only) Allegro(R) PCB RF option
Allegro(R) PCB SI - GXL Cadence 3D Design Viewer option
Allegro Package Designer XL Allegro Package SI L
Allegro(R) AMS Simulator (Windows only) Allegro(R) Design Entry HDL - XL
Allegro(R) PCB SI - XL Allegro(R) PCB PI option - XL
Allegro(R) PCB Librarian - XL Allegro(R) Physical Viewer
Allegro(R) PCB Design HDL - XL Allegro(R) PCB Router - XL

Combined IC and Systems Package:

From IUS 8.1.006-sUSR1:
Verifault®-XL simulator 64bit Verifault®-XL simulator
Cadence® Export Model Packager AMS Designer with Flexible Analog Simulation
From IPCM Hotfix 8.1.004:
Incisive Plan-to-Closure Methodology Option
From EMGR 8.1003:
Incisive Enterprise Manager
From SPMN 8.1.003:
Incisive Enterprise Specman ESL Testbench
From IFV Hotfix 8.1.004:
Incisive Formal Verifier
From ABVIPAHB 1.0:
AMBA AHB Assertion Based VIP
From ABVIPAXI 1.0:
AMBA AXI Assertion Based VIP
From ABVIPOCP 2.2:
OCP-IP Assertion Based VIP
From UVCAMBA 2.4:
AMBA AHB UVC
From UVCAXI 1.4:
AMBA AXI UVC
From EVCETH 2.2:
e Verification Component (eVC) for Ethernet protocol
From EVCPCI 2.2:
e Verification Component (eVC) for PCI 2.2/2.3 protocol
From UVCPCIE 3.0:
PCI Express 2.0 End Point UVC PCI Express 2.0 Root Complex UVC
From UVCUSB 2.5:
USB UVC
From ANLS 7.1 USR2:
Dynamic Gate Option to VoltageStorm PE VoltageStorm PE
From ASSURA3.1.7 USR2HF10_CDB:
Assura(TM) Design Rule Checker Assura(TM) Layout Vs. Schematic Verifier
Assura(TM) Parasitic Extractor Assura(TM) RCX Field Solver Option
Assura(TM) RCX Parasitic Inductance Option Assura(TM) RCX Multiprocessor Option
Assura(TM) RCX High Frequency Option RCX Advanced process features
Assura(TM) Multiprocessor Option
From ASSURA3.1.7 USR2HF7OA_612:
Assura(TM) Design Rule Checker Assura(TM) Layout Vs. Schematic Verifier
Assura(TM) Parasitic Extractor Assura(TM) RCX Field Solver Option
Assura(TM) RCX Parasitic Inductance Option Assura(TM) RCX Multiprocessor Option
Assura(TM) RCX High Frequency Option RCX Advanced process features
Assura(TM) Multiprocessor Option
From CCD 7.2 s300:
Encounter Conformal Constraint Designer - XL
From CONFRML 7.2 Hotfix s340:
Encounter Conformal Low Power - GXL Encounter Conformal ECO Designer
From ET 7.2.4:
Encounter(R) True-time Test - GXL Encounter(R) Test Architect - GXL
Encounter Diagnostics Environment - XL Encounter Diagnostics Engine - XL
From ETS 7.1 USR3-s218_1:
Encounter Library Characterizer - GXL Encounter Timing System-GXL
From EXT 7.12:
Virtuoso QRC Extraction - GXL
From IC 5.1.41 Hotfix 122:
Cadence(R) Design Framework II Cadence(R) Design Framework Integrator's Toolkit
64bit Cadence(R) Design Framework Integrator's Toolkit Virtuoso(R) Preview
Virtuoso(R) Simulation Environment Virtuoso(R) Schematic VHDL Interface
Virtuoso(R) Schematic Editor Verilog(R) Interface Virtuoso(R) Schematic Editor HSPICE Interface
64bit Virtuoso(R) Layout Editor Virtuoso(R)-XL Layout Editor
Virtuoso(R) Compactor Virtuoso LE Turbo Basic
Virtuoso(R) Analog Oasis Run-Time Option Cadence(R) OASIS for RFDE
Virtuoso(R) Electronic Design for Manufacturability Option Spectre(R) Third-party Simulator Interface
Spectre(R) Verilog-A Simulation Option Spectre(R)/-RF - Cadence(R) SPW Model Link Option to Spectre(R) RF
Spectre(R)-RF IC Package Modeler Option Virtuoso(R) Analog HSPICE Interface Option
Virtuoso(R) Schematic Editor Virtuoso(R) Analog Design Environment
Spectre(R)-RF Substrate Coupling Analysis Option Virtuoso(R) Analog VoltageStorm Option
Virtuoso(R) Analog ElectronStorm Option Virtuoso(R) Layout Migrate
Structure Compiler Virtuoso(R) Schematic Composer to design compiler integration
Cadence(R) RC Network Reducer Option Virtuoso(R) AMS Designer Environment
Dracula(R) Design Rule Checker 64bit Dracula(R) Design Rule Checker
Dracula(R) Layout Vs. Schematic Verifier 64bit Dracula(R) Layout Vs. Schematic Verifier
Dracula(R) Parasitic Extractor 64bit Dracula(R) Parasitic Extractor
64bit Diva(R) Design Rule Checker Diva(R) Layout Vs. Schematic Verifier
64bit Diva(R) Layout Vs. Schematic Verifier Diva(R) Parasitic Extractor
Cadence(R) SKILL Development Environment Virtuoso(R) EDIF 300 Connectivity Reader/Writer
Virtuoso(R) EDIF 300 Schematic Reader/Writer 64bit Virtuoso(R) STREAM Interface
Cadence(R) team design project administrator
From IC IC 6.1.3:
Cadence(R) Design Framework II Cadence(R) Design Framework Integrator's Toolkit
64bit Cadence(R) Design Framework Integrator's Toolkit Virtuoso(R) Simulation Environment
Virtuoso(R) Schematic VHDL Interface Virtuoso(R) Schematic Editor Verilog(R) Interface
Virtuoso(R) Schematic Editor HSPICE Interface Virtuoso(R) Analog Oasis Run-Time Option
Cadence(R) OASIS for RFDE Virtuoso(R) Analog HSPICE Interface Option
Virtuoso(R) Analog VoltageStorm Option Virtuoso(R) Analog ElectronStorm Option
Virtuoso(R) Layout Migrate Cadence(R) RC Network Reducer Option
Virtuoso(R) AMS Designer Environment Dracula(R) Design Rule Checker
64bit Dracula(R) Design Rule Checker Dracula(R) Layout Vs. Schematic Verifier
64bit Dracula(R) Layout Vs. Schematic Verifier Dracula(R) Parasitic Extractor
64bit Dracula(R) Parasitic Extractor Diva(R) Design Rule Checker
64bit Diva(R) Design Rule Checker Diva(R) Layout Vs. Schematic Verifier
64bit Diva(R) Layout Vs. Schematic Verifier Diva(R) Parasitic Extractor
Cadence(R) SKILL Development Environment Virtuoso(R) EDIF 200 Reader
Virtuoso(R) EDIF 200 Writer Virtuoso(R) Schematic Editor XL
Virtuoso(R) Analog Design Environment - GXL Virtuoso(R) Visualization & Analysis XL
64bit Virtuoso(R) Layout Suite L Virtuoso(R) Layout Suite - GXL
Virtuoso Constraint API Run-Time Option CDLIN
PostScript Level 2 Hardcopy Output
From ICC 11.2.41 Hotfix 60:
Virtuoso(R) Chip Assembly Router
From MMSIM 7.01 Hotfix 076:
Virtuoso(R) Spectre Model Interface Option Spectre(R)/-RF - Cadence(R) SPW Model Link Option to Spectre(R) RF+G199
Virtuoso(R) UltraSim Full-chip Simulator Virtuoso(R) RelXpert
Cadence Virtuoso Passive Component Designer Virtuoso Spectre GXL
From AES 1.0:
Cadence Advanced Encryption Standard-64bit
From RFDSGN 3.0.3.001:
Virtuoso RF Designer
From REL SOC 7.1 USR3-s219_1:
SoC Encounter - GXL
From SPB Hotfix 16.01.016:
Cadence(R) SKILL Development Environment Allegro(R) System Architect - GXL
Allegro(R) PCB Partitioning option (SPARC/Solaris only) Allegro(R) PCB RF option
Allegro(R) PCB SI - GXL Cadence 3D Design Viewer option
Allegro Package Designer XL Allegro Package SI L
Allegro(R) AMS Simulator (Windows only) Allegro(R) Design Entry HDL - XL
Allegro(R) PCB SI - XL Allegro(R) PCB PI option - XL
Allegro(R) PCB Librarian - XL Allegro(R) Physical Viewer
Allegro(R) PCB Design HDL - XL Allegro(R) PCB Router - XL

PCB Studio:

From SPB Hotfix 16.01.016:
Allegro(R) AMS Simulator Allegro(R) PCB Design CIS - L
Allegro(R) PCB Performance option - L Allegro(R) PCB SI - L

Optional Package 1:

From SPB Hotfix 16.01.016:
Cadence SiP Digital Architect - GXL Cadence SiP Digital SI XL
Cadence SiP Digital Layout GXL Cadence SiP RF Architect - XL
Cadence SiP RF Layout GXL

Supported Machine Types

SUN SPARC Solaris 2 (sun4v), Windows XP Professional (PCB Studio Tools and subset of Systems Tools only) and X86 Redhat LINUX (lnx86)

Note that not all modules are available on all platforms. Please contact the EUROPRACTICE Software Service for details.

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STFC Home page The EUROPRACTICE Software Service is managed by the Microelectronics Support Centre, Rutherford Appleton Laboratory, UK.

You can contact the EUROPRACTICE Software Service by email: enquiries@msc.rl.ac.uk

Last modified: December 2, 2008.

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