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Cadence 2009/2010 Release |
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Quick links:
| IC Package | Combined IC and Systems Package | Optional Package 1 |
| Systems Package | PCB Studio | Supported Machine Types |
| From IES 8.2/Hotfix 019: | |
| Incisive Enterprise Simulator - XL (licence only) | ESL Option For Incisive Enterprise Simulator - XL (licence only) |
| Enterprise Simulator - XL Interface For MTI (licence only) | Enterprise Simulator - XL Interface For VCS (licence only) |
| From KITSOCV 8.2/USR1: | |
| IP Verification Kit (Licensed through IES 8.2 licences) | |
| From IUS 8.2/ Hotfix 015: | |
| Verifault(R)-XL simulator | 64bit Verifault(R)-XL simulator |
| Cadence(R) Export Model Packager | Digital Mixed Signal Option to IES |
| AMS Designer with Flexible Analog Simulation (includes NCSim, NCSC, Verilog-XL) | |
| From EMGR 8.2/Hotfix 008: | |
| Incisive Enterprise Manager | |
| From SPMN 8.2/USR3: | |
| Incisive Enterprise Specman ESL Testbench (Licensed through IES 8.2 licences) | |
| From IFV 8.2/Hotfix 014: | |
| Incisive Formal Verifier | |
| From VIPP 8.2/USR1: | |
| Incisive VIP Portfolio | |
| From AMSD 8.2: | |
| Virtuoso AMS Designer Verification Option (licence only) | |
| From CCD 8.1/Update 8.1-s400: | |
| Encounter Conformal Constraint Designer - XL | |
| From CONFRML 8.1/Hotfix 440: | |
| Encounter Conformal Low Power - GXL | Encounter Conformal ECO Designer - GXL |
| From ET 8.1/8.1.200 Update: | |
| Encounter Diagnostics Environment - XL | Encounter Diagnostics Engine - XL |
| Architect Advanced Option to RC | Encounter True Time Test Advanced |
| From ETS 8.1/USR2: | |
| Encounter Library Characterizer - GXL | Encounter Power System XL |
| EPS Advanced Analysis GXL Option | Encounter Timing System-XL |
| ETS Advanced Analysis GXL Option | |
| From EXT 8.1/8.14 Update: | |
| Virtuoso QRC Extraction - GXL | |
| From RC 8.1/Hotfix 205: | |
| Encounter RTL Compiler - GXL option | Encounter RTL Compiler with physical |
| From SOC 8.1/USR2: | |
| Encounter Low Power GXL Option | Encounter Mixed Signal GXL Option |
| Encounter Digital Implementation System XL | Encounter Advanced Node GXL Option |
| From ASSURA 3.2-CDB/Hotfix 11: | |
| Assura(TM) Design Rule Checker | Assura(TM) Layout Vs. Schematic Verifier |
| Assura(TM) Multiprocessor Option | |
| From IC 5.1.41/Hotfix 137: | |
| Cadence(R) Design Framework II | Cadence(R) Design Framework Integrator's Toolkit |
| 64bit Cadence(R) Design Framework Integrator's Toolkit | Virtuoso(R) Simulation Environment |
| Virtuoso(R) Schematic VHDL Interface | Virtuoso(R) Schematic Editor Verilog(R) Interface |
| Virtuoso(R) Schematic Editor HSPICE Interface | 64bit Virtuoso(R) Layout Editor |
| Virtuoso(R)-XL Layout Editor | Virtuoso(R) Compactor |
| Virtuoso LE Turbo Basic | Virtuoso(R) Analog Oasis Run-Time Option |
| Cadence(R) OASIS for RFDE | Virtuoso(R) Electronic Design for Manufacturability Option |
| Spectre(R) Third-party Simulator Interface | Virtuoso(R) Analog HSPICE Interface Option |
| Virtuoso(R) Schematic Editor | Virtuoso(R) Analog Design Environment |
| Virtuoso(R) Analog VoltageStorm Option | Virtuoso(R) Analog ElectronStorm Option |
| Virtuoso(R) Layout Migrate | Virtuoso(R) Schematic Composer to design compiler integration |
| Virtuoso(R) AMS Designer Environment | Dracula(R) Design Rule Checker |
| 64bit Dracula(R) Design Rule Checker | Dracula(R) Layout Vs. Schematic Verifier |
| 64bit Dracula(R) Layout Vs. Schematic Verifier | Dracula(R) Parasitic Extractor |
| 64bit Dracula(R) Parasitic Extractor | Diva(R) Design Rule Checker |
| 64bit Diva(R) Design Rule Checker | Diva(R) Layout Vs. Schematic Verifier |
| 64bit Diva(R) Layout Vs. Schematic Verifier | Diva(R) Parasitic Extractor |
| Cadence(R) SKILL Development Environment | Virtuoso(R) EDIF 300 Connectivity Reader/Writer |
| Virtuoso(R) EDIF 300 Schematic Reader/Writer | 64bit Virtuoso(R) STREAM Interface |
| From IC 6.1.3/Hotfix 13: | |
| Cadence(R) Design Framework II | Cadence(R) Design Framework Integrator's Toolkit |
| 64bit Cadence(R) Design Framework Integrator's Toolkit | Virtuoso(R) Simulation Environment |
| Virtuoso(R) Schematic VHDL Interface | Virtuoso(R) Schematic Editor Verilog(R) Interface |
| Virtuoso(R) Schematic Editor HSPICE Interface | Virtuoso(R) Analog Oasis Run-Time Option |
| Cadence(R) OASIS for RFDE | Virtuoso(R) Analog HSPICE Interface Option |
| Virtuoso(R) Chip Assembly Router | Virtuoso(R) Analog VoltageStorm Option |
| Virtuoso(R) Analog ElectronStorm Option | Virtuoso(R) Layout Migrate |
| Virtuoso(R) AMS Designer Environment | Dracula(R) Design Rule Checker |
| 64bit Dracula(R) Design Rule Checker | Dracula(R) Layout Vs. Schematic Verifier |
| 64bit Dracula(R) Layout Vs. Schematic Verifier | Dracula(R) Parasitic Extractor |
| 64bit Dracula(R) Parasitic Extractor | Diva(R) Design Rule Checker |
| 64bit Diva(R) Design Rule Checker | Diva(R) Layout Vs. Schematic Verifier |
| 64bit Diva(R) Layout Vs. Schematic Verifier | Diva(R) Parasitic Extractor |
| Cadence(R) SKILL Development Environment | Virtuoso(R) EDIF 200 Reader |
| Virtuoso(R) EDIF 200 Writer | Virtuoso(R) Schematic Editor XL |
| Virtuoso(R) Analog Design Environment - GXL | Virtuoso(R) Visualization & Analysis XL |
| 64bit Virtuoso(R) Layout Suite L | Virtuoso(R) Layout Suite XL |
| Virtuoso(R) Layout Suite - GXL | Virtuoso Constraint API Run-Time Option |
| From ICS 6.1.2: | |
| Virtuoso(R) Layout Suite - GXL (licence only) | |
| From ICC 11.2.41/Hotfix 66: | |
| Virtuoso(R) Chip Assembly Router | |
| From MMSIM 7.1/Hotfix 188: | |
| Virtuoso(R) Spectre Model Interface Option | Virtuoso(R) UltraSim Full-chip Simulator |
| Virtuoso(R) RelXpert | Virtuoso Spectre GXL |
| Virtuoso Accelerated Parallel Simulator - XL | |
| From AES 1.0: | |
| Cadence Advanced Encryption Standard-64bit (licence only) | |
| From PVS 8.0/Hotfix 8.20.001: | |
| Cadence(R) Physical Verification System - L | |
| From KQV 5.1/Hotfix 003: | |
| Cadence(R) QuickView Mask and Layout Data Viewer | |
| From IES 8.2/Hotfix 019: | |
| Incisive Enterprise Simulator - XL (licence only) | ESL Option For Incisive Enterprise Simulator - XL (licence only) |
| Enterprise Simulator - XL Interface For MTI (licence only) | Enterprise Simulator - XL Interface For VCS (licence only) |
| From KITSOCV 8.2/USR1: | |
| IP Verification Kit (Licensed through IES 8.2 licences) | |
| From IUS 8.2/ Hotfix 015: | |
| Verifault(R)-XL simulator | 64bit Verifault(R)-XL simulator |
| Cadence(R) Export Model Packager | Digital Mixed Signal Option to IES |
| AMS Designer with Flexible Analog Simulation (includes NCSim, NCSC, Verilog-XL) | |
| From EMGR 8.2/Hotfix 008: | |
| Incisive Enterprise Manager | |
| From SPMN 8.2/USR3: | |
| Incisive Enterprise Specman ESL Testbench (Licensed through IES 8.2 licences) | |
| From IFV 8.2/Hotfix 014: | |
| Incisive Formal Verifier | |
| From VIPP 8.2/USR1: | |
| Incisive VIP Portfolio | |
| From AMSD 8.2: | |
| Virtuoso AMS Designer Verification Option (licence only) | |
| From SPB 16.2/Hotfix 018: | |
| Cadence(R) SKILL Development Environment | Allegro(R) System Architect - GXL |
| Allegro(R) PCB Partitioning option | Allegro(R) PCB RF option |
| Allegro PCB Interconnect Flow Designer Option - XL (licence only) | Allegro PCB Interconnect Feasibility Option - XL (licence only) |
| Allegro PCB Global Route Environment Option - XL (licence only) | Allegro(R) PCB SI - GXL |
| Cadence 3D Design Viewer option | Allegro Package Designer XL |
| Allegro Package SI L | Allegro(R) AMS Simulator (Windows only) |
| Allegro(R) Design Entry HDL - XL | Allegro(R) PCB SI - XL |
| Allegro(R) PCB PI option - XL | Allegro(R) PCB Librarian - XL |
| Allegro(R) Physical Viewer | Allegro(R) PCB Design HDL - XL |
| Allegro(R) PCB Router - XL | |
| From IES 8.2/Hotfix 019: | |
| Incisive Enterprise Simulator - XL (licence only) | ESL Option For Incisive Enterprise Simulator - XL (licence only) |
| Enterprise Simulator - XL Interface For MTI (licence only) | Enterprise Simulator - XL Interface For VCS (licence only) |
| From KITSOCV 8.2/USR1: | |
| IP Verification Kit (Licensed through IES 8.2 licences) | |
| From IUS 8.2/ Hotfix 015: | |
| Verifault(R)-XL simulator | 64bit Verifault(R)-XL simulator |
| Cadence(R) Export Model Packager | Digital Mixed Signal Option to IES |
| AMS Designer with Flexible Analog Simulation (includes NCSim, NCSC, Verilog-XL) | |
| From EMGR 8.2/Hotfix 008: | |
| Incisive Enterprise Manager | |
| From SPMN 8.2/USR3: | |
| Incisive Enterprise Specman ESL Testbench (Licensed through IES 8.2 licences) | |
| From IFV 8.2/Hotfix 014: | |
| Incisive Formal Verifier | |
| From VIPP 8.2/USR1: | |
| Incisive VIP Portfolio | |
| From AMSD 8.2: | |
| Virtuoso AMS Designer Verification Option (licence only) | |
| From CCD 8.1/Update 8.1-s400: | |
| Encounter Conformal Constraint Designer - XL | |
| From CONFRML 8.1/Hotfix 440: | |
| Encounter Conformal Low Power - GXL | Encounter Conformal ECO Designer - GXL |
| From ET 8.1/8.1.200 Update: | |
| Encounter Diagnostics Environment - XL | Encounter Diagnostics Engine - XL |
| Architect Advanced Option to RC | Encounter True Time Test Advanced |
| From ETS 8.1/USR2: | |
| Encounter Library Characterizer - GXL | Encounter Power System XL |
| EPS Advanced Analysis GXL Option | Encounter Timing System-XL |
| ETS Advanced Analysis GXL Option | |
| From EXT 8.1/8.14 Update: | |
| Virtuoso QRC Extraction - GXL | |
| From RC 8.1/Hotfix 205: | |
| Encounter RTL Compiler - GXL option | Encounter RTL Compiler with physical |
| From SOC 8.1/USR2: | |
| Encounter Low Power GXL Option | Encounter Mixed Signal GXL Option |
| Encounter Digital Implementation System XL | Encounter Advanced Node GXL Option |
| From ASSURA 3.2-CDB/Hotfix 11: | |
| Assura(TM) Design Rule Checker | Assura(TM) Layout Vs. Schematic Verifier |
| Assura(TM) Multiprocessor Option | |
| From IC 5.1.41/Hotfix 137: | |
| Cadence(R) Design Framework II | Cadence(R) Design Framework Integrator's Toolkit |
| 64bit Cadence(R) Design Framework Integrator's Toolkit | Virtuoso(R) Simulation Environment |
| Virtuoso(R) Schematic VHDL Interface | Virtuoso(R) Schematic Editor Verilog(R) Interface |
| Virtuoso(R) Schematic Editor HSPICE Interface | 64bit Virtuoso(R) Layout Editor |
| Virtuoso(R)-XL Layout Editor | Virtuoso(R) Compactor |
| Virtuoso LE Turbo Basic | Virtuoso(R) Analog Oasis Run-Time Option |
| Cadence(R) OASIS for RFDE | Virtuoso(R) Electronic Design for Manufacturability Option |
| Spectre(R) Third-party Simulator Interface | Virtuoso(R) Analog HSPICE Interface Option |
| Virtuoso(R) Schematic Editor | Virtuoso(R) Analog Design Environment |
| Virtuoso(R) Analog VoltageStorm Option | Virtuoso(R) Analog ElectronStorm Option |
| Virtuoso(R) Layout Migrate | Virtuoso(R) Schematic Composer to design compiler integration |
| Virtuoso(R) AMS Designer Environment | Dracula(R) Design Rule Checker |
| 64bit Dracula(R) Design Rule Checker | Dracula(R) Layout Vs. Schematic Verifier |
| 64bit Dracula(R) Layout Vs. Schematic Verifier | Dracula(R) Parasitic Extractor |
| 64bit Dracula(R) Parasitic Extractor | Diva(R) Design Rule Checker |
| 64bit Diva(R) Design Rule Checker | Diva(R) Layout Vs. Schematic Verifier |
| 64bit Diva(R) Layout Vs. Schematic Verifier | Diva(R) Parasitic Extractor |
| Cadence(R) SKILL Development Environment | Virtuoso(R) EDIF 300 Connectivity Reader/Writer |
| Virtuoso(R) EDIF 300 Schematic Reader/Writer | 64bit Virtuoso(R) STREAM Interface |
| From IC 6.1.3/Hotfix 13: | |
| Cadence(R) Design Framework II | Cadence(R) Design Framework Integrator's Toolkit |
| 64bit Cadence(R) Design Framework Integrator's Toolkit | Virtuoso(R) Simulation Environment |
| Virtuoso(R) Schematic VHDL Interface | Virtuoso(R) Schematic Editor Verilog(R) Interface |
| Virtuoso(R) Schematic Editor HSPICE Interface | Virtuoso(R) Analog Oasis Run-Time Option |
| Cadence(R) OASIS for RFDE | Virtuoso(R) Analog HSPICE Interface Option |
| Virtuoso(R) Chip Assembly Router | Virtuoso(R) Analog VoltageStorm Option |
| Virtuoso(R) Analog ElectronStorm Option | Virtuoso(R) Layout Migrate |
| Virtuoso(R) AMS Designer Environment | Dracula(R) Design Rule Checker |
| 64bit Dracula(R) Design Rule Checker | Dracula(R) Layout Vs. Schematic Verifier |
| 64bit Dracula(R) Layout Vs. Schematic Verifier | Dracula(R) Parasitic Extractor |
| 64bit Dracula(R) Parasitic Extractor | Diva(R) Design Rule Checker |
| 64bit Diva(R) Design Rule Checker | Diva(R) Layout Vs. Schematic Verifier |
| 64bit Diva(R) Layout Vs. Schematic Verifier | Diva(R) Parasitic Extractor |
| Cadence(R) SKILL Development Environment | Virtuoso(R) EDIF 200 Reader |
| Virtuoso(R) EDIF 200 Writer | Virtuoso(R) Schematic Editor XL |
| Virtuoso(R) Analog Design Environment - GXL | Virtuoso(R) Visualization & Analysis XL |
| 64bit Virtuoso(R) Layout Suite L | Virtuoso(R) Layout Suite XL |
| Virtuoso(R) Layout Suite - GXL | Virtuoso Constraint API Run-Time Option |
| From ICS 6.1.2: | |
| Virtuoso(R) Layout Suite - GXL (licence only) | |
| From ICC 11.2.41/Hotfix 66: | |
| Virtuoso(R) Chip Assembly Router | |
| From MMSIM 7.1/Hotfix 188: | |
| Virtuoso(R) Spectre Model Interface Option | Virtuoso(R) UltraSim Full-chip Simulator |
| Virtuoso(R) RelXpert | Virtuoso Spectre GXL |
| Virtuoso Accelerated Parallel Simulator - XL | |
| From AES 1.0: | |
| Cadence Advanced Encryption Standard-64bit (licence only) | |
| From PVS 8.0/Hotfix 8.20.001: | |
| Cadence(R) Physical Verification System - L | |
| From KQV 5.1/Hotfix 003: | |
| Cadence(R) QuickView Mask and Layout Data Viewer | |
| From SPB 16.2/Hotfix 018: | |
| Cadence(R) SKILL Development Environment | Allegro(R) System Architect - GXL |
| Allegro(R) PCB Partitioning option | Allegro(R) PCB RF option |
| Allegro PCB Interconnect Flow Designer Option - XL (licence only) | Allegro PCB Interconnect Feasibility Option - XL (licence only) |
| Allegro PCB Global Route Environment Option - XL (licence only) | Allegro(R) PCB SI - GXL |
| Cadence 3D Design Viewer option | Allegro Package Designer XL |
| Allegro Package SI L | Allegro(R) AMS Simulator (Windows only) |
| Allegro(R) Design Entry HDL - XL | Allegro(R) PCB SI - XL |
| Allegro(R) PCB PI option - XL | Allegro(R) PCB Librarian - XL |
| Allegro(R) Physical Viewer | Allegro(R) PCB Design HDL - XL |
| Allegro(R) PCB Router - XL | |
| SPB 16.2/Hotfix 018 (Windows only): | |
| Allegro(R) PCB Partitioning option | Allegro® Design Entry CIS |
| Allegro(R) AMS Simulator | Allegro(R) PCB Design CIS - L |
| Allegro(R) PCB Performance option - L | Allegro(R) PCB SI - L |
| SPB 16.2/Hotfix 018 (x86/Linux & SPARC/Solaris only): | |
| Cadence SiP Digital Architect - GXL | Cadence SiP Digital SI XL |
| Cadence SiP Digital Layout GXL | Cadence SiP RF Architect - XL |
| Cadence SiP RF Layout GXL | |
Note that not all modules are available on all platforms. Please contact the EUROPRACTICE Software Service for platform and operating system details.
 |
The EUROPRACTICE Software Service is managed by the
Microelectronics Support Centre, Rutherford Appleton Laboratory,
UK.
You can contact the EUROPRACTICE Software Service by email: enquiries@msc.rl.ac.uk Last modified: December 9, 2009. |