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May 2009
Xilinx V11.1
Xilinx System Edition 11.1 has been released. This Xilinx System Edition package includes
Key features of the new release include availability of the full suite of Xilinx software as a single package for all EUROPRACTICE members, FLEXnet licensing, reduced runtime through increased synthesis and place and route performance, and tighter integration between ISE, PlanAhead and ChipScope and EDK.
The site representative for existing EUROPRACTICE Xilinx sites will automatically receive a license entitlement via the ‘Xilinx download and licensing website’ within the next few days. If your license entitlement is not yet available, a 60 day trial license can be activated to allow you to get started with Xilinx System Edition V11.1.
Full details can be found via the Software Links above.
Introduction of XUPV5-LX110T Development Board
The XUPV5-LX110T is a versatile general purpose FPGA development board. Based on the Xilinx ML505 board, the XUPV5 includes a larger Virtex-5 LX110T FPGA. The LX110T Virtex-5 with over 100,000 logic cells, 64 DSP48E slices, 148 36Kbit block rams, PCI Express and high speed transceivers, provides high performance programmable logic capability.
Please note that 1 Platform USB II Cable is supplied with each each XUPV5-LX110T board purchased.
Full details can be found via the Hardware Links above.
Xilinx System Edition, which contains the full suite of Xilinx software, is now available to all EUROPRACTICE members. All existing Xilinx users will be automatically entitled to upgrade to this version at no additional cost.
Xilinx software is available by download. For existing Xilinx users, if you are the EUROPRACTICE site rep, or an authorized user, please go to the Xilinx Product Download and Licensing Site where you may download, install, license products, or authorize additional users to access the download site.
To access the Xilinx Download and Licensing Site, please click here
System requirements:
* System Generator & AccelDSP are not supported under Linux
If you require a DVD, please go to the download site to request a DVD.
Please note, Xilinx 11.1 does not support Virtex, Virtex II, Virtex II Pro or Spartan 2 devices. If you wish to use these devices, please continue to use version 10.1.
Click here for Xilinx 11.1 release notes and documentation.
Xilinx System Edition package
| ISE Foundation | ISE Foundation is a complete logic design environment, comprising design capture, synthesis, verification and implementation software. |
| PlanAhead | PlanAhead provides IO pin planning, floor planning, design analysis and supports partial reconfiguration for complex and high performance FPGA designs. |
| ChipScope Pro | ChipScope allows on-chip debug by providing visibility of internal FPGA signals, including embedded processor buses, for real time verification of FPGA designs. ChipScope Pro is also compatible with logic analyser hardware from Agilent. |
| EDK | EDK is a development environment for hardware/software co-design based around the PowerPC and Microblaze processor cores. A license for the Microblaze IP is also included as part of this package. Microblaze is the Xilinx 32-bit soft processor core and comes complete with a standard set of peripherals (e.g. UART, memory interface), GNU compiling and debugging tools. Microblaze can be used on the all Xilinx FPGA families. |
| System Generator | System Generator enables designers to develop high-performance DSP systems for Xilinx FPGAs using MATLAB and Simulink. System Generator, through Simulink, provides a graphical modelling environment for generation of bit-accurate models of FPGA circuits, and automatically generates synthesizable Hardware Description Language (HDL) code. A library of IP for use in Simulink is included with System Generator. |
| AccelDSP | AccelDSP synthesis tool is a high-level MATLAB language based tool for designing DSP blocks for Xilinx FPGAs. AccelDSP can generate synthesizable HDL and fixed point C++ models and automatically converts floating point to fixed point. |
*Note that ModelSim Xilinx Edition (MXE) is not supported via EUROPRACTICE. EUROPRACTICE users can obtain the more capable ModelSim SE via the Mentor Graphics pages on this web site.
Xilinx Hardware is only available for purchase via EUROPRACTICE. Please note, to order any Xilinx Hardware, you must be an in maintenance Xilinx ISE Software user with licences via EUROPRACTICE, or apply to be so at the time of the order for Xilinx Hardware.
XUPV5-LX110T Development Board
The XUPV5-LX110T is a versatile general purpose FPGA development board. Based on the Xilinx ML505 board, the XUPV5 includes a larger Virtex-5 LX110T FPGA. The LX110T Virtex-5 with over 100,000 logic cells, 64 DSP48E slices, 148 36Kbit block rams, PCI Express and high speed transceivers, provides high performance programmable logic capability.
The XUPV5 development board is also the recommended platform for OpenSPARC development. OpenSPARC is the open source version of Sun's UltraSPARC T1 and T2 microprocessors which are current commercial multi-threaded multi-core microprocessors. Full synthesizable source code is available for the T1 and T2 processors though the OpenSPARC program.
A Xilinx EDK reference design of a single core OpenSPARC T1 is available for the XUPV5-LX110T Development Board.
For more details and kit contents, please click on the image on the left.
Further information can be found at http://www.xilinx.com/univ/xupv5-lx110t.htm
For OpenSPARC information please visit the EUROPRACTICE and Sun Microsystems OpenSPARC pages.
Please note that 1 Platform USB II Cable is supplied with each each XUPV5-LX110T board purchased.
Please note that the EUROPRACTICE Software Service aims to maintain a small stock of these boards for shipment on receipt of order. Sites ordering these boards should receive them ahead of any software being ordered, which will be batched up into the next monthly order in the normal manner.
Platform USB II Cable
The Platform USB II cable, permits programming of all Xilinx devices, on-chip debug via ChipScope Pro Analyser, and configuration of other devices in the JTAG chain such PROM, Flash, or system ACE.
A Platform USB II Cable is recommended for use with ChipScope Pro and EDK
Please note that 1 Platform USB II Cable is supplied with each each XUPV5-LX110T board purchased, although any number of Cables can be purchased independently.
From version 11.1, Xilinx will use FLEXnet for licensing. Floating and node locked licenses are available.
Xilinx licenses are managed by the EUROPRACTICE site representative, or authorized user, through the Xilinx website. The site representative/authorized user can generate floating or node-locked license files as required from the pool of available licenses. It is not necessary to specify the type of license required when placing an order.
Please go to the Xilinx Download and Licensing Site to manage your licenses.
The EUROPRACTICE Software Service place bulk orders with Vendors monthly. In order to be included on the monthly order, Institute orders to EUROPRACTICE must be received at RAL by no later than the 25th day of each month.
Xilinx Donation applications will be processed on a case by case basis, after receipt of all required documentation.
Detailed instructions on how to place a EUROPRACTICE software order, how to complete the order forms and the financial procedures that must be followed are given in the Software Order Procedures.
Useful documents:PLEASE ensure that you read the Instructions for Completing the End User Agreements before downloading the Agreements.
Xilinx will donate Xilinx Software to educational institutions on a case-by-case basis for new course laboratories for educational and non-commercial purposes only. Donation approvals will normally be determined by Xilinx within one month of receipt by Xilinx.
PLEASE ensure that you read the End User Agreement Notes before downloading the End User Agreements.
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The EUROPRACTICE Software Service is managed by the
Microelectronics Support Centre, Rutherford Appleton Laboratory,
UK.
You can contact the EUROPRACTICE Software Service by email: enquiries@msc.rl.ac.uk Last modified: November 2, 2009. |
